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Features
* * * * * * *
6.5 m x 6.5 m Photodiode Pixel, at 6.5 m Pitch 2 x 2 Outputs High Output Data Rate: 4 x 5 MHz High Dynamic Range: 10000: 1 Antiblooming and Exposure Time Control Very Low Lag 56 lead 0.6" DIL Package
Description
Atmel's TH7834C is a linear sensor based on charge-coupled device (CCD) technology. It can be used in a wide range of applications thanks to operating mode flexibility, very high definition and high dynamic range (document scanning, digital photography, Art, Industrial and Scientific Applications).
Pixel 1 mark VOS1 VDR1 VS1 R1-2 VSS VST A1-2 VGS1-2 VS 3A 1A 4A 2A VSS VSS 2C 4C 1C 3C VSS P3-4 VA3-4 LS3-4 VSS VDD3-4 VS3 VDR3 VOS3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VOS2 VDR2 VS2 VDD1-2 VSS LS1-2 VA1-2 P1-2 VSS 3D 1D 4D 2D VSS VSS 2B 4B 1B 3B VSS VGS3-4 A3-4 VST VSS R3-4 VS4 VDR4 VOS4
Very Highresolution Linear CCD Image Sensor (12000 Pixels) TH7834C
TOP VIEW
Rev. 1997A-IMAGE-05/02
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Pin Description
Pin Number 1 2 3 4 5, 9, 14, 15, 20, 24, 33, 37, 42, 43, 48, 52 6, 34 7 8 10 11 12 13 16 17 18 19 21 22 23 25 26 27 28 29 30 31 32 35 36 38 39 40 41 44 45 Symbol VOS1 VDR1 VS1 R1-2 VSS VST A1-2 VGS1-2 3A 1A 4A 2A 2C 4C 1C 3C P3-4 VA3-4 LS3-4 VDD3-4 VS3 VDR3 VOS3 VOS4 VDR4 VS4 R3-4 A3-4 VGS3-4 3D 1D 4D 2D 2B 4B Designation Output 1 (Odd Pixels) Reset DC Bias (Output 1) Amplifier Source Bias (Output 1) Reset Clock (Outputs 1 and 2) Substrate Bias (Ground) Pixel Storage Gate DC Bias Antiblooming and/or Exposure Time Control Output Gate DC Bias Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock Transfer Clock Antiblooming Diode Bias Register End Transport Clock Amplifier Drain Supplies (Outputs 3, 4) Amplifier Source Bias (Output 3) Reset DC Bias (Output 3) Output 3 (Odd Pixels) Output 4 (Even Pixels) Reset DC Bias (Output 4) Amplifier Source Bias (Output 4) Reset Clock (Outputs 3 and 4) Antiblooming and/or Exposure Time Control Output Gate DC Bias Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock Register Main Transport Clock
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TH7834C
Pin Description (Continued)
Pin Number 46 47 49 50 51 53 54 55 56 Notes: Symbol 1B 3B P1-2 VA1-2 LS1-2 VDD1-2 VS2 VDR2 Designation Register Main Transport Clock Register Main Transport Clock Transfer Clock Antiblooming Diode Bias Register End Transport Clock Amplifier Drain Supplies (Outputs 1, 2) Amplifier Source Bias (Output 2) Reset DC Bias (Output 2)
VOS2 Output 2 (Even Pixels) 1. Pins A1-2, VGS1-2, P1-2, VA1-2, LS1-2, VDD1-2, R1-2 and respectively, A3-4, VGS3-4, P3-4, VA3-4, LS3-4, VDD3-4, R3-4 are not connected together inside the package. 2. Two Pins VST connected together inside the package.
Figure 1. TH7834 Block Diagram
3B VS2 VDR2 LS1-2 1B 4B 2B 2D 4D 1D 3D
VGS3-4
VDR4
VS4
VOS2 P1-2
CCD
B
CCD
D
VOS4 VST
VDD1-2 R1-2 VST P3-4 R3-4 1 12000 VDD3-4
VOS1
CCD
A
CCD
C
VOS3
VS1
VDR1
VGS1-2
3A
1A 4A
2A 2C
4C 1C
3C
LS3-4
VDR3
VS3
Description
TH7834C high resolution linear array consists of 12000 useful pixel photosensitive line, associated with four CCD shift registers and four output amplifiers. Transfer gates on both sides of the photosensitive line enable delivery of charges, respectively: * * on one side, charge accumulated by odd pixels (1, 3, 5... 11999), to CCD shift registers A and C, on the other side, charge accumulated by even pixels (2, 4, 6... 12000), to CCD shift registers B and D.
Shift registers 1 and 2 collect charges generated by one half of the photosensitive line (pixel 1 to 6000), whereas shift registers 3 and 4 collect charges generated by the second half of the photosensitive line (pixels 12000 to 6001).
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The four CCD shift registers have separated clocks. The output signal can be, then, delivered simultaneously or sequentially on the four outputs. The four CCD shift registers are designed with 4 separated gates. According to the gate connection, the signal can be read through 2 or 4 output amplifiers. According to gate connection, 2 or 4 output operating mode can be chosen. In the 4 output operating mode, signals associated to the end pixels of the array (either pixels number 1, 2 or pixels number 11999, 12000) are delivered first in time and signals corresponding to the center of the line (pixels number 5999, 6000 and 6001, 6002) are delivered last in time. Thus, external circuitry and processing are needed to combine the four video outputs and to restore the normal order of the pixels in accordance with their spatial distribution on the photosensitive line. Terminal stages for every CCD shift register have separate clock control inputs in order to speed up the final charge to voltage conversion and reduce the video output settling time. Antiblooming and exposure time control functions are provided. Symmetrical TH7834 package PIN OUT allow to inverted pin 1 and 56 positions without damage. To obtain optimal operating mode, separated driving circuits are recommended for each readout shift register (at least LS and R). Figure 2. Driving Schematic
Logical signal : L1 L2 Logical signal : L1 L2
Pins (1,2,3,4)B
Pins (1,2,3,4)D
VOS2
2
CCD B
6000 6002
CCD D 12000
VOS4
Photosensitive line
VOS1
1
CCD A
5999 6001
CCD C 11999
VOS3
Pins F(1,2,3,4)A
Pins F(1,2,3,4)C
PHI3C
Logical signal : L1
L2
Logical signal : L1
L2
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TH7834C
Readout Shift Register Clocking
All gates of the 4 CCD shift registers are separated, enabling two or four output readout modes. To select 2 or 4 outputs operating mode, register main transport gates must be connected as described here after: * 4 outputs mode: VOS1: L1 = 2A + 3A; L2 = 1A + 4A VOS2: L1 = 2B + 3B; L2 = 1B + 4B VOS3: L1 = 2C + 3C; L2 = 1C + 4C VOS4: L1 = 2D + 3D; L2 = 1D + 4D * 2 output mode: VOS1 and VOS2: VOS1: L1 = 2A + 3A + 1C + 2C
L2 = 1A + 4A + 3C + 4C
VOS2: L1 = 2B + 3B + 1D + 2D
L2 = 1B + 4B + 3D + 4D
*
2 output mode: VOS3 and VOS4: VOS3: L1 = 1A + 2A + 2C + 3C
L2 = 3A + 4A + 1C + 4C
VOS4: L1 = 1B + 2B + 2D + 3D
L2 = 3B + 4B + 1D + 4D Note: In 2 output mode, the unused outputs can be connected as following: * LS = R = VGS = 0V * 10V < VDR < 15V * VDD = 15V * VS not connected in order to cancel unused output amplifiers power consumption.
Absolute Maximum Ratings*
Storage Temperature ................................... -55C to + 150C Operating Temperature ................................. 0C to + 70C *NOTICE: Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect reliability.
Thermal Cycling.........................................................15C/mm Maximum Voltage: * Pins: 4, 6, 7, 8, 10, 11, 12, 13, 16, 17, 18, 19, 21, 23, 32, 34, 35, 36, 38, 39, 40, 41, 44, 45, 46, 47, 49, 51...............................................-0.3V to + 15V * Pins: 2, 3, 22, 25, 26, 27, 30, 31, 50, 53, 54, 55............................................-0.3V to + 15.5V * Pins: 5, 9, 14, 15, 20, 24, 33, 37, 42, 43, 48, 52 .. Ground 0V
Operating Range
Operating range defines the temperature limits between which the functionality is guaranteed: 0C to 70C.
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Operating Precautions
Shorting the video outputs to VSS or VDD, even temporarily, can permanently damage the output amplifiers.
Operating Conditions (T = 25C)
Table 1. DC Characteristics
Value Parameter Output Amplifier Drain Supply Substrate Voltage Reset DC Bias Output Amplifier Source Bias Output Gate DC Bias Photosensitive Zone DC Bias Antiblooming Diode Bias Note: Symbol VDD1-2, VDD3-4 VSS VDR1, VDR2, VDR3, VDR4 VS1, VS2, VS3, VS4 VGS1-2, VGS3-4 VST VA1-2, VA3-4 2.2 3.5 14 Min. 14.5 0 Typ. 15 0 VDD - 0.5 0 2.4 4 14.5 2.6 4.5 15 Max. 15.5 Unit V V V V V V V
If no exposure time control is required, A1-2 and A3-4 must be connected to an adjustable DC bias (see Figure 7). Typical current in VDR, VA < 10 A; in VGS, VST < 1 A.
Timing Diagram
Figure 3. Line Timing Diagram
P1-2 P3-4 L1, L2 LS1-2, LS3-4 R1-2, R3-4 Ec1 (clamp) External Ech (Sampling) Detailed timing diagram for transfert from photosite to register (see fig. 4) Detailed pixel timing diagram (see fig. 5) Cleaning Readout time for line M Integration time Ti for line M+1
Pixel N
*
Note:
Minimum exposure time: Ti min = readout time. 3043 For data rate of 5 MHz: Ti min = ---------------- = 608.6 s. 5 MHz
It is better to clean the shift registers (with running clocks) and not to stop clocking them after readout time.
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* Each video line in four output operating mode consists in: - - - - - 30 inactive pre-scan, (not connected to pixels), 6 dark references, 4 isolation elements, (inactive, not connected to pixels), 3 non-useful pixels, 3 000 useful pixels of the line.
N = number of pixel periods (Tp) during readout period (see Figure 5). Four output operating mode: N 3043. Two output operating mode: N 6086. (LS can be clocked during the line blancking). Figure 4. Detailed Timing Diagram For Transfer From Photosite To Register
P1-2, P3-4 20 ns L1, L2 LS N R 1 2 s 100 ns
Figure 5. Detailed Pixel Timing Diagram
P1-2, P3-4 L1, L2 Tp/2 Typ. LS1-2, LS3-4 R1-2, R3-4 20 ns 30 ns Tp (200 ns Typ.)
VOS (1-2-3-4) (CCD output signal)
Reset Floating diode (Reference level for correlated double Sampling)
Signal
TP = Pixel period Rise and fall time:
R1-2, R3-4: 5% of TP (min. 5 ns), LS1-2, LS3-4: 5% of TP (min. 5 ns), L1, L2: 25% of TP (min. 30 ns), P1-2, P3-4: 100 ns (min 20 ns).
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Cross over of complementary clocks (L1 and L2) preferably at 50% of their amplitude.
Note: Generally, the difference between the floating diode level and signal level is the sum of several signals: * Register clock feedthrough * Average CCD register dark signal proportional to CCD clock period, mode, temperature * Pixel dark signal (depending upon temperature and exposure time) * Pixel signal under illumination
Table 2.
Elements Signals Register Clock Feedthrough Average CCD Register Dark Signal Pixel Dark Signal Pixel Signal Under Illumination Inactive Prescan X X Dark References X X X Isolation Elements X X Non Useful Pixels X X X X
Useful Pixels X X X X
Table 3. Drive Clock Voltage Swings
Value Parameter Register Main Transport Clock(1) Symbol L1, L2 LS1-2, LS3-4 A1-2, A3-4 Logic High Low High Low High Antiblooming (Low Level) And Exposure Time Control (High Level)(1) Low High Low High Low Min. 8.5 0 8.5 0 9.5 0 10.5 0 10.5 0 Typ. 9 0.4 9 0.2 10 To be adjusted 11 1.5 11 0.4 12.5 2 11.5 0.6 Max. 11 0.6 11 0.4 10.5 Unit V V V V V V V V V V
Register End Transport Clock(1)
Reset Clock(1)
R1-2, R3-4 P1-2, P3-4
Transfer Clock(1) Note:
1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase of the dark signal. If such spurious negative transients are present, they can be removed by inserting a serial resistor of appropriate value (typically 20 to 100 ) at the relevant driver output.
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Table 4. Drive Clock Capacitances Operating Frequencies(1)
Symbol Function/Clock Capacitive Network
L1 160pF L2
Total L1: 570 pF L2: 640 pF for one CCD(1) 50 pF per phase
Max. Frequency
L1, L2
Register Main Transport Clock
250pF
320pF
10 MHz
LS1-2, LS3-4
Register End Transfer Clock
P 15pF 15pF
10 MHz Pulse duration 2 s Period: 608.6 s (4 outputs mode)
P1-2, P3-4
Transfer Clock
VST 50pF VSS 15pF
L2
80 pF per phase
A1-2, A3-4
Antiblooming And Exposure Time Control
A 60pF VSS
VST
100 pF per phase
Reset Clock R1-2, R3-4 Note: 1. For 1/4 of total CCD register.
50 pF per phase
10 MHz
Table 5. Static and Dynamic Electrical Characteristics
Value Parameter DC Output Level (Pins: 1, 28, 29, 56) Output Impedance (Pins: 1, 28, 29, 56) Maximum Data Output Frequency Per Channel Input Current On Active Pins 4, 6, 7, 8, 10, 11, 12, 13, 16, 17, 18, 19, 21, 23, 32, 34, 35, 36, 38, 39, 40, 41, 44, 45, 46, 47, 49, 51 Amplifier Drain Supply Current (Per VDD) Symbol Vref ZS FS max Min. Typ. 10 400 5 600 10 Max. Unit V MHz
(Note:)
Remarks
Ie
<< 1
2
A
Vin = 15V with all other pins = 0V VDD = 15V
IDD1-2, IDD3-4
10
16
mA
Static Power Dissipation (Per VDD) PD1-2, PD3-4 165 240 mW Note: The maximum clock frequency is limited by the dark signal increase. Full performance for 5 MHz.
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Electro-optical Performance
* *
General measurement conditions: Tc = 25C; Ti = 1 ms; FLA, FLB, FLC, FLD = 5 MHz, readout through 4 outputs. Light source: tungsten filament lamp (2,854 K) + BG 38 filter (2 mm thick) + F/3.5 aperture. The BG 38 filter limits the spectrum to 700 nm. In these conditions, 1 J/cm2 corresponds to 3.5 lux.s. Typical operating conditions (see Table 1, 2, 3 and 4). First and last pixels of the photosensitive line, as well as reference elements, are excluded from the specification. Test without antiblooming, except for AE max.
*
* Table 6. Electro-optical Performance
Value Parameter Saturation Output Voltage With Antiblooming OFF Saturation Exposure Responsitivity Photo Response Non-uniformity Excluding Single Defects Contrast Transfer Function At Nyquist Frequency (77 Ip/mm) at 500 nm at 600 nm at 700 nm Temporal Noise In Darkness (rms) Dynamic Range (Relative to rms Noise) Pixel Average Dark Signal Dark Signal Non-uniformity Register Single Stage Transfer Efficiency Lag (Vertical Charge Transfer Efficiency) DR VDS DSNU 1- VCTE 0.99998 Symbol VSAT ESAT R PRNU 3.5 Min. 2 Typ. 3 0.6 5 6 10 Max. Unit V J/cm2 V/J/cm2 % VOS VOS = 1.0V(4) Remarks
(1)(2)(3)
CTF
75 62 47 300 10000 110 90 0.999998 0.1 0.5 250 400
% % % V
VOS = 1.5V For white level
(5)
V/ms V/ms
(6)
Peak to peak(6) VOS = 1V
%
(7)
(8) Antiblooming Efficiency AE max <1 15 mV Notes: 1. Value measured with respect to zero reference level. 2. Conversion factor is typically: 6 V/e-. 3. Without antiblooming: A1-2 = A3-4 = 0V. 4. VOS = average output voltage; PRNU for each output, in 4 output operating mode. 5. Measured in Correlated Double Sampling (C.D.S.) mode. 6. VDS and DSNU vary with temperature. 7. Residual signal after line readout, at VOS= 1V. 8. Line acquisition with Phi-A at high level. AE max = maximum signal along the line (to test all the antiblooming sites).
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Figure 6. Typical Spectral Responsitivity
8.0 =0.8 7.2 =0.6 6.4 5.6 =0.7
(V/J/cm 2)
4.8 4.0 3.2 2.4 1.6 0.8 0 400 500 600 700 800 900 1000 1100
Lambda (nm)
Figure 7. VSAT versus A Low Level Typical Curve
Antiblooming OFF 3600 3400 3200 3000 2800 2600 2400 2200 2000 1800 1600 1400 1200 1000 800 600 400 200 0 0 1 2 3 4 Antiblooming ON
VST = 4 V R Low level = 1.5V VA = 13V
Vsat. (mV)
5
6
7
8 8.5
A bias (V)
Exposure Time Reduction (See Figure 8)
TH7834 allows a reduction in the exposure time without changing the readout time. It thus provides a function which is equivalent to an optical iris. The exposure time reduction consists in increasing the A gate bias in order to remove continuously, during period 2, the photoelectrons from the pixel and to inject them into the antiblooming diode VA. When A returns to the normal bias, electrons are integrated in the pixel. Only excess electrons are evacuated into VA (blooming control). Thus, the actual integration time is ti instead of Ti, without any change in the readout sequence. Register transfer and reset clocks (L, LS and R) must be pulsed during the Ti integration time.
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Table 7. Exposure Time Reduction Conditions
Value Parameter Antiblooming Diode Bias Antiblooming And Expose Time Control Period 1 Period 2 Symbol VA1-2. VA3-4 A1-2, A3-4 Min. 14 Typ. 15.5 to be adjusted Max. 15 Unit V V
9.5
10
10.5
V
Figure 8. Timing Diagram For Exposure Time Control
P(1-2, 3,4) A(1-2, 3,4) 0V Clear period Period 2 Period 1 t 20ns
Antiblooming level
TR
integration time ti
TR = Readout period
Note:
It is better to have A falling/rising edge outside the useful readout period.
Outline Drawing
2.54 0.25 3.15 0.32 1.10 0.10
PIXEL 1 MARK 1
4.35 0.45
2.12 0.27
3 2
1.27 0.25
3.2 9.71 0.6
4.2 68.58 0.25 (2.54 x 27)
15.24 0.25
Z=1.800.30 88.0 0.88.
1 Y 2 3
Window Photosensitive area Optical distance between external face of window and photosensitive area
7.50 0.10
X
5.00 0.10
1st pixel
pixel 12000 |Y12000-Y1| 150 m
Note:
Antireflective window: reflection. Less than 1% per side over 400 - 700 nm wavelength range. All dimensions are in mm (except otherwise specified).
Ordering Code
12
The ordering code is TH7834CCC-RB
TH7834C
1997A-IMAGE-05/02
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
1997A-IMAGE-05/02 0M

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